The present invention relates to a method for driving an inverter device.
FIG. 1 is a diagram showing a prior known drive circuit of an inverter circuit, wherein this circuit is configured including a first direct current (DC) power supply 1, a upper semiconductor switching element 2 connected to a positive polarity side of the first DC power supply 1, a second drive circuit 4 for turn-on/off drive of the upper switching element 2, and a capacitor 7 for supplying a drive voltage to the drive circuit 4 when this capacitor 7 is charged. This circuit configuration is generally known as the "bootstrap" circuit. During the turn-on period of a lower semiconductor switching element 3 connected to a negative polarity side of the first DC power supply 1, a voltage at an output terminal of FIG. 1 becomes substantially equal to a voltage on the negative side of the first DC power supply 1 so that a circuit for charging and supplying electrical charge to the capacitor 7 from a second DC power supply 6, which is a drive power supply of a first drive circuit 5 for on/off-driving the lower semiconductor switching element 3 connected to the negative polarity side, is provided via a route indicated by dotted line portions in FIG. 1.
The final charge-up voltage being charged by this circuit at the capacitor 7 becomes nearly equal to the voltage of the second DC power supply 6 thereby enabling this capacitor 7 to be directly used as a drive power supply of the second drive circuit 4 which causes the upper semiconductor switching element 2 coupled to the positive polarity side to turn on and off.
Next, one exemplary prior art in the aforementioned configuration is shown in FIG. 2.
The circuit shown in FIG. 2 is designed such that a voltage monitoring circuit 9 is provided for monitoring a voltage between both terminals of the capacitor 7 while also providing an operation function of protecting the upper semiconductor switching element 2 by preventing turn-on of the upper semiconductor switching element 2 connected to the positive polarity side in cases where the capacitor 7 is low in voltage potential, thus eliminating thermal destruction or breakdown otherwise occurring due to turn-on of the upper semiconductor switching element 2 which operates in the state that the drive voltage is kept low in potential (Published Unexamined Japanese Patent Application or "PUJPA" No. 3-150075).
Incidentally, in most cases, it will hardly occur during normal operations that the charged voltage of the capacitor 7 in FIG. 2 becomes lower then a voltage value as set at the voltage monitoring circuit 9, except that this occurs exclusively at a specific time when the capacitor 7 undergoes an initial charge-up at the beginning of start-up of an inverter operation in the inverter device.
Under the features stated above, further in the inverter device, with regard to a means for transferring turn-on/off drive signals to an on/off drive circuit of an upper arm-side semiconductor switching element, another problem occurs in the case where the device employs an on/off signal edge transfer/latch scheme using a drive signal transfer section 12 for use with the upper arm-side semiconductor switching element which section contains therein a high breakdown voltage IC 11 as shown in FIG. 3, rather than continuous signal transfer schemes based on the turn-on/off of a photo-coupler that has been traditionally employed as electrical insulation means, as will be discussed below.
Upon startup of the inverter operation of the inverter device, a lower arm-side semiconductor switching element is typically held in the turn-on state continuously for along time period in order to increase the charge up speed of the capacitor 7. On the other hand, in view of the fact that the turn-on/off signal transmission of the upper arm-side semiconductor switching element follows the edge transfer/latch scheme, where the turn-on signal is accidentally latched during this initial charge up period due to malfunction of the upper arm-side semiconductor switching element drive signal transfer section 12, or alternatively due to externally applied "invasion" noises, both the upper and lower arm-side semiconductor switching elements turn on simultaneously resulting in the upper-and-lower electrical short-circuit state. At this time, since the voltage of the capacitor 7 stays low in potential in the midway of such initial charge up operation, the upper arm-side semiconductor switching element using this capacitor 7 as its drive power supply turns on due to deficiency of the drive voltage resulting in an operation in an unsaturated state, which in turn leads to unwanted concentration of heat loss which can cause damage or destruction. In addition, in the ease mentioned above, an over current detecting circuit 14 that is inherently provided for protection from the upper-and-lower short circuiting is limited in current because of operation in such an unsaturated state, and thus is unable to function in an expected way.
One possible approach to avoidance of this problem is to employ a prior art capacitor charge up monitoring circuit which is operable to prevent turn-on of the upper arm-side semiconductor switching element while the capacitor voltage remains low within the initial charge up time period to thereby eliminate latching of the turn-on signal. However, it will possibly happen that the setup voltage value of this voltage monitor circuit is slightly low in setup voltage in view of possible deviation in the manufacture thereof. If this is the case, latching of the turn-on signal of the upper arm-side semiconductor switching element can take place immediately after the capacitor charge up voltage goes beyond a preset voltage value V.sub.r of the voltage monitor circuit as shown in FIG. 4, thereby causing both the upper and lower arm-side semiconductor switching elements to turn on resulting in a current being suppressed at a level at which the over current defector circuit does not yet exhibit its intended function when the upper-and-lower short circuiting occurs. This in turn causes a problem of an inability to protect the upper arm-side semiconductor switching element. In FIG. 4 the reference character V.sub.o designates the voltage which enables the over current detector circuit to function, and V.sub.c denotes the final charge up voltage value of the capacitor. (A) indicates a time period in which the voltage monitoring circuit offers reliable protecting ability, that is, the period in which the over current detector circuit is incapable of protection; (B) is a time period in which the voltage monitor circuit does not offer reliable protection, namely, the period in which the over current detector circuit is incapable of protection; (C) is a period in which the over current circuit offers reliable protection, i.e., the period in which the voltage monitor circuit fails to offer reliable protection; and, (D) is a period in which the over current detector circuit offers reliable protection, i.e., the period in which the voltage monitor circuit cannot protect.